Assess chip‑design skill, not keyword matches
Test RTL design, verification, physical design and embedded firmware with questions built for hardware: circuit and block diagrams, written design reasoning, and code.
Design Verification Engineer · question 5 of 18
Built from the job description
Draw a static CMOS NAND2, then design the waveform for Y across eight cycles.
Schematic editordrag to place · click to wire
Waveform editor1 div = 5 ns
Y matches ~(A·B) on all 8 cycles
EvaluationStrong
Circuit and timing correct; parasitic delay under-counted
Key results4 of 5 match
Boolean function~(A·B)~(A & B)
PMOS width22
Logical effort g4/34/3
Parasitic delay p2τ1τ
Circuit correctness · 40%5/5
Timing behaviour · 35%5/5
Delay analysis · 25%3/5
Strengths
Correct pull-up and pull-down topology · Y matches the truth table on all 8 cycles
Gaps
Parasitic delay counts one diffusion; the output node sees two
What a test for this role can look like
One example. You choose the sections, the question types, the length and how closely it is watched.
- Draft it from a job description, or build it by hand
- Review every question before a candidate sees it
- Reuse questions from your own bank
Design Verification Engineer — 2 to 5 years
SystemVerilog and UVM
- Duration
- 75min
- Sections
- 5
- Questions
- 26
- 01×20
Digital design and SystemVerilog fundamentals
Multiple choice - 02×1
Draw the testbench architecture for a given DUT
Draw it - 03×1
Draw the FSM for a handshake protocol
Draw it - 04×3
Explain a coverage-closure and debug approach
Written, marked by AI - 05×1
Scripting task for log parsing
Write and run codePython or C++
Proctoring: Webcam + screen + phone camera, CheqMate AI
Why generic tests fail chip-design hiring
- 01
Generic coding tests miss hardware skill
An algorithm puzzle says little about whether someone can write clean RTL, build a UVM testbench or close timing. Hardware roles need hardware questions.
- 02
A small pool makes every wrong rejection expensive
There are only so many verification or physical-design engineers on the market. A screen that rejects a good engineer on a technicality costs you weeks.
- 03
Senior engineers spend their time on first rounds
Your design leads are the only people who can judge the answers, so they end up interviewing candidates who should have been filtered out earlier.
- 04
Remote tests invite outside help
Design questions with well-known answers are easy to look up or pass to a friend. You need to know the candidate worked alone.
From an open req to a shortlist
- 1
Build the test by domain
Combine multiple-choice fundamentals, diagram questions, written design questions and coding. Generate a first draft from the job description, then have your engineers review it.
- 2
Let candidates draw and explain
Candidates draw circuits, block diagrams and state machines, and explain their design choices in their own words.
- 3
Proctor the session
Webcam, screen and TriNetra’s second camera watch every session, and CheqMate AI stops AI assistants throughout.
- 4
Review scored answers, not raw scripts
Written answers are marked by AI that knows hardware. Your engineers see the score, the reasoning and the answer side by side, and can override any score.
Roles you can assess
- RTL design engineer
- Design verification engineer (SystemVerilog, UVM)
- Physical design engineer
- DFT engineer
- Analog and mixed-signal design engineer
- STA and timing engineer
- FPGA engineer
- Embedded C and firmware engineer
- Post-silicon validation engineer
- CAD and EDA engineer
- Campus graduate trainee (ECE, EEE)
Common questions
Which hardware domains can we test?
TalentDecrypt is built for RTL design, design verification, physical design, DFT, analog design and embedded firmware. Write questions in your own domain, and written answers are marked with hardware know-how, not a generic rubric.
Can candidates write and simulate HDL code?
The coding editor runs general-purpose languages such as C, C++, Python and Java, which suits embedded C, firmware and scripting questions. HDL and design knowledge is tested with diagram, written and multiple-choice questions.
How do we stop a good engineer being rejected by the AI score?
The AI marks first and shows its reasoning beside the answer. Your engineer can change any score, and theirs is the one that stands.
Does it work for campus hiring as well as lateral?
Yes. The same platform runs a large campus batch with a live proctoring wall, and a single senior candidate with a harder, longer test.
See it with one of your own roles
Bring a job description to the demo. We will build the test with you and show you the report a candidate produces.